Linux Makefile: Automating Compilation and Linking

A Makefile is a file used in Linux to automate the compilation and linking process of a program. It contains a set of instructions or rules that specify how to compile and link the source files into an executable program.

Here is an example of a simple Makefile for a C program:

CC = gcc
CFLAGS = -Wall -g

TARGET = myprogram
OBJS = main.o utils.o

all: $(TARGET)

$(TARGET): $(OBJS)
	$(CC) $(CFLAGS) -o $@ $^

%.o: %.c
	$(CC) $(CFLAGS) -c $< -o $@

clean:
	rm -f $(OBJS) $(TARGET)

In this Makefile, the 'CC' variable specifies the compiler to be used (gcc), and the 'CFLAGS' variable defines the compiler flags ('-Wall' for enabling all warning messages, and '-g' for including debugging information).

The 'TARGET' variable specifies the name of the executable program, and the 'OBJS' variable lists the object files required for linking.

The 'all' rule is the default target, which depends on the '$(TARGET)' rule.

The '$(TARGET)' rule depends on the '$(OBJS)' rule, and it compiles and links the object files into the final executable program. The '$@' and '$^' are automatic variables that represent the target and dependencies, respectively.

The '%.o: %.c' rule is a pattern rule that describes how to compile a C source file into an object file. The '$<' automatic variable represents the first dependency (the C source file), and '$@' represents the target (the object file).

The 'clean' rule is used to clean up the generated object files and the executable program.

To use this Makefile, simply save it as 'Makefile' in the same directory as your source code files and run the 'make' command in the terminal. It will automatically compile and link the source files into the executable program specified in the 'TARGET' variable.