FPGA Verilog 实现四位二进制信号到两位数码管输出 (0-15)

module binary_to_bcd( input [3:0] binary_in, output [6:0] bcd_out );

// Define the BCD values for each binary value
reg [3:0] bcd_values [15:0];
initial
begin
    bcd_values[0] = 4'b0000;
    bcd_values[1] = 4'b0001;
    bcd_values[2] = 4'b0010;
    bcd_values[3] = 4'b0011;
    bcd_values[4] = 4'b0100;
    bcd_values[5] = 4'b0101;
    bcd_values[6] = 4'b0110;
    bcd_values[7] = 4'b0111;
    bcd_values[8] = 4'b1000;
    bcd_values[9] = 4'b1001;
    bcd_values[10] = 4'b0000;
    bcd_values[11] = 4'b0000;
    bcd_values[12] = 4'b0000;
    bcd_values[13] = 4'b0000;
    bcd_values[14] = 4'b0000;
    bcd_values[15] = 4'b0000;
end

// Convert the binary input to BCD output
assign bcd_out = {bcd_values[binary_in]};

endmodule