Verilog 实现 10-12、60-80、120-159 计数器拉高输出

module counter ( input clk, output reg out );

reg [7:0] count;

always @(posedge clk) begin if ((count >= 10 && count <= 12) || (count >= 60 && count <= 80) || (count >= 120 && count <= 159)) out = 1; else out = 0;

count <= count + 1;

end

endmodule