Hot Carrier Effects in MOSFETs for RF Circuit Design: Understanding and Mitigation

Hot Carrier Effects in MOSFETs for RF Circuit Design: Understanding and Mitigation

With the continual scale-down of the channel length of MOSFETs and on-chip passive devices such as inductors with good performance parameters, CMOS technology has become a viable choice for the implementation of radio frequency (RF) circuit blocks such as low noise amplifiers (LNA), oscillators and mixers [1–8]. By reducing the channel length of MOSFETs, however, the issues related to short channel effects such as drain induced barrier lowering (DIBL) [9], punch-through and hot carriers become important [10].

In NMOSFETs, applying the biasing voltages to the device's terminals naturally leads to the appearance of electric fields inside the device. In the saturation mode of operation, in a part of the channel near drain known as the pinch-off region, the inversion layer almost completely disappears and the electric field in this region is significantly higher than that in the rest of the channel [11]. When the carriers enter this region, they gain high energy and therefore are called hot carriers.

As hot-carriers flow toward the drain, some of them collide with the silicon atoms and generate new electron—hole pairs. This process is called avalanche, similar to the breakdown of a reverse biased pn junction. The new electrons and holes generated during the avalanche process are swept by the drain and substrate terminals, respectively. The current flowing through the substrate terminal is called Isub.

During the avalanche process, hot carriers can also impinge on the atomic bonds between silicon and silicon dioxide (SiO2) in the gate oxide layer, causing damage and degradation of device performance [12–14]. Therefore, it is crucial to understand and mitigate the impact of hot carrier effects in MOSFETs for RF circuit design.