Verilog 中 wire [3:0] mem_write_enable 化简: rd_en = ~(&(~mem_write_enable))

Verilog 中，wire [3:0] mem_write_enable; \nrd_en = ~(&(~mem_write_enable)) 化简后，是什么内容：rd_en = ~(&(~mem_write_enable)) 的化简结果是 rd_en = mem_write_enable[0] & mem_write_enable[1] & mem_write_enable[2] & mem_write_enable[3]。