Verilog 中 mem_write_enable 信号化简：rd_en 的逻辑简化

Verilog 中，wire [3:0] mem_write_enable; \nrd_en = (~mem_write_enable[0] & ~mem_write_enable[1] & ~mem_write_enable[2] & ~mem_write_enable[3]) 化简后，是什么内容：化简后的结果是 rd_en = ~(mem_write_enable[0] | mem_write_enable[1] | mem_write_enable[2] | mem_write_enable[3])。