Verilog 中 wire [3:0] mem_write_enable 化简：rd_en 表达式优化
Verilog 中，wire [3:0] mem_write_enable; \nrd_en = ~mem_write_enable[0] & ~mem_write_enable[1] & ~mem_write_enable[2] & ~mem_write_enable[3]) 化简后，是什么内容：化简后的表达式是：\n\nrd_en = ~(mem_write_enable[0] | mem_write_enable[1] | mem_write_enable[2] | mem_write_enable[3])
![Verilog 中 wire [3:0] mem_write_enable 化简：rd_en 表达式优化](http://copyright.bdstatic.com/vcg/creative/69300db26cd9a4741e30bed766c8c4ae.jpg "Verilog 中 wire [3:0] mem_write_enable 化简：rd_en 表达式优化")
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