SystemVerilog 中逻辑表达式化简：mem_write_enable & read_valid

SystemVerilog 中，logic [3:0] mem_write_enable; logic read_valid; assign rd_en = ~(~(&(~mem_write_enable)) | (~read_valid))；化简后，是什么内容：化简后的表达式是 rd_en = mem_write_enable & read_valid;