FPGA实现四位二进制信号到两位数码管输出(0-15) - 代码示例

以下是一个使用FPGA实现输入四位二进制信号并在两位数码管输出的代码示例：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity BinaryToBCD is
    port (
        binary_input : in std_logic_vector(3 downto 0);
        bcd_output   : out std_logic_vector(3 downto 0)
    );
end entity;

architecture Behavioral of BinaryToBCD is
begin
    process(binary_input)
    begin
        case binary_input is
            when '0000' =>
                bcd_output <= '0000';
            when '0001' =>
                bcd_output <= '0001';
            when '0010' =>
                bcd_output <= '0010';
            when '0011' =>
                bcd_output <= '0011';
            when '0100' =>
                bcd_output <= '0100';
            when '0101' =>
                bcd_output <= '0101';
            when '0110' =>
                bcd_output <= '0110';
            when '0111' =>
                bcd_output <= '0111';
            when '1000' =>
                bcd_output <= '1000';
            when '1001' =>
                bcd_output <= '1001';
            when '1010' =>
                bcd_output <= '1010';
            when '1011' =>
                bcd_output <= '1011';
            when '1100' =>
                bcd_output <= '1100';
            when '1101' =>
                bcd_output <= '1101';
            when '1110' =>
                bcd_output <= '1110';
            when '1111' =>
                bcd_output <= '1111';
            when others =>
                bcd_output <= '0000'; -- Default case
        end case;
    end process;
end architecture;

上述代码定义了一个名为BinaryToBCD的实体，它有一个四位二进制输入binary_input和一个四位二进制输出bcd_output。BinaryToBCD的体系结构定义了一个处理过程，根据输入的二进制值设置输出的BCD值。在这个例子中，通过使用一个简单的case语句，将每个二进制值映射到对应的BCD值。如果输入的二进制值不在0到15的范围内，输出将设置为默认值'0000'。