Verilog Module: exam2 - A Simple D-Flip-Flop with Reset

The provided Verilog code implements a simple D-flip-flop with an active-low reset, named 'exam2'. The module takes a clock signal ('clk'), an active-low reset signal ('rst_n'), and an input data signal ('data_in'). The output data is stored in the 'data_out' register.

module exam2 (
  input clk,
  input rst_n,
  input data_in,
  output reg data_out
);

  always @(posedge clk) begin
    if (!rst_n)
      data_out <= 1'b0;
    else
      data_out <= data_in;
  end

endmodule

RTL Structure Diagram

The RTL structure diagram depicts the functionality of the module. Here's the diagram for 'exam2':

       __________
clk -->|          |
       |   exam2  |
rst_n -->|          |
data_in->|          |
       |          |
data_out<--|__________|

Explanation:

• clk: This represents the clock signal, which triggers the flip-flop's behavior.
• rst_n: The active-low reset signal. When low, it forces the output to 0.
• data_in: The input data signal that is loaded into the flip-flop on the clock's rising edge.
• data_out: The output data signal, which holds the current value of the flip-flop.

The 'exam2' module essentially implements a D-flip-flop with a synchronous reset. On the positive edge of the clock, the output 'data_out' is either reset to 0 (if 'rst_n' is low) or updated with the input data 'data_in' (if 'rst_n' is high).