Verilog 计数器实现特定范围拉高输出

module counter ( input wire clk, input wire reset, output wire out );

reg [7:0] count;

always @(posedge clk or posedge reset) begin
    if (reset)
        count <= 0;
    else if (count >= 10 && count <= 12)
        count <= count + 1;
    else if (count >= 60 && count <= 80)
        count <= count + 1;
    else if (count >= 120 && count <= 159)
        count <= count + 1;
    else
        count <= 0;
end

assign out = (count >= 10 && count <= 12) || (count >= 60 && count <= 80) || (count >= 120 && count <= 159);

endmodule