Verilog实现公式round((2^d * x)/3329) mod 2^d

module mod_calc(\n input wire [31:0] x,\n input wire [4:0] d,\n output wire [31:0] result\n);\n\nreg [31:0] prod;\nreg [31:0] quotient;\nreg [31:0] remainder;\n\nalways @(*) begin\n prod = (2**d) * x;\n quotient = prod / 3329;\n remainder = prod % 3329;\n result = remainder;\nend\n\nendmodule