STM8S003F3 驱动配置头文件 - DRV_CFG.H - 常规

#ifndef\u0020_DRV_CFG_H\n#define\u0020_DRV_CFG_H\n\n//-------------------------------------------------------------------------------------\n//\u0020系统参数设置\n#define\u0020FMASTER\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u002016000000\n#define\u0020CLOCK_TICK\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020250//us\u0020\u0020\u0020\u0020//ms\n\n//-------------------------------------------------------------------------------------\n//\u0020系统单片机型号\n#define\u0020_STM8S003F3\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(1)\n\n//-------------------------------------------------------------------------------------\n//\u0020开发环境\n#define\u0020_ST_IAR\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(1)\n#define\u0020__DI()\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020asm\u0020("SIM")\n#define\u0020__EI()\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020asm\u0020("RIM")\n\n//-------------------------------------------------------------------------------------\n//\u0020MCU模块配置\n#define\u0020_M_DRV\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(0x1000)\n#define\u0020_M_DRV_CHK\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV+0x01)\n\n//\u0020MCU\n#define\u0020_M_DRV_MCU\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV+0x100)\n#define\u0020_M_DRV_MCU_INIT\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV+0x100+1)\n\n//\u0020CPU\n#define\u0020_M_DRV_MCU_CPU\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV+0x100)\n#define\u0020_M_DRV_MCU_CPU_RST\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_CPU+1)\n#define\u0020_M_DRV_MCU_CPU_CHK\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_CPU+2)\n\n//\u0020Clock\n#define\u0020_M_DRV_MCU_CPU_CLK_INIT\u0020(_M_DRV_MCU_CPU+3)\n#define\u0020_M_DRV_MCU_CPU_CLK_CHK\u0020(_M_DRV_MCU_CPU+4)\n\n//\u0020WDT\n#define\u0020_M_DRV_MCU_CPU_WDT\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_CPU+5)\n#define\u0020_M_DRV_MCU_CPU_IWDG\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_CPU+6)\n#define\u0020_M_DRV_MCU_CPU_WWDG\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_CPU+7)\n#define\u0020_M_DRV_MCU_CPU_WDT_CHK\u0020(_M_DRV_MCU_CPU+8)\n\n//\u0020PORT\n#define\u0020_M_DRV_MCU_PORT\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV+0x200)\n#define\u0020_M_DRV_MCU_PORT_INIT\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT+1)\n#define\u0020_M_DRV_MCU_PORT_CHK\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT+2)\n#define\u0020_M_DRV_MCU_PORT_CHK_SHORT\u0020(0)//(_M_DRV_MCU_PORT+3)\n\n#define\u0020_M_DRV_MCU_PORT_0\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT+1)\n#define\u0020_M_DRV_MCU_PORT_1\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT+2)\n#define\u0020_M_DRV_MCU_PORT_2\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT+3)\n#define\u0020_M_DRV_MCU_PORT_3\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT+4)\n#define\u0020_M_DRV_MCU_PORT_4\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_PORT+5)\n#define\u0020_M_DRV_MCU_PORT_5\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_PORT+6)\n#define\u0020_M_DRV_MCU_PORT_6\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_PORT+7)\n\n#define\u0020_M_DRV_MCU_PORT_CR1\u0020\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT+10)\n#define\u0020_M_DRV_MCU_PORT_0_CR1\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT_CR1+1)\n#define\u0020_M_DRV_MCU_PORT_1_CR1\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT_CR1+2)\n#define\u0020_M_DRV_MCU_PORT_2_CR1\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT_CR1+3)\n#define\u0020_M_DRV_MCU_PORT_3_CR1\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT_CR1+4)\n#define\u0020_M_DRV_MCU_PORT_4_CR1\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_PORT_CR1+5)\n#define\u0020_M_DRV_MCU_PORT_5_CR1\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_PORT_CR1+6)\n#define\u0020_M_DRV_MCU_PORT_6_CR1\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_PORT_CR1+7)\n\n#define\u0020_M_DRV_MCU_PORT_CR2\u0020\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT+20)\n#define\u0020_M_DRV_MCU_PORT_0_CR2\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT_CR2+1)\n#define\u0020_M_DRV_MCU_PORT_1_CR2\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT_CR2+2)\n#define\u0020_M_DRV_MCU_PORT_2_CR2\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT_CR2+3)\n#define\u0020_M_DRV_MCU_PORT_3_CR2\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_PORT_CR2+4)\n#define\u0020_M_DRV_MCU_PORT_4_CR2\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_PORT_CR2+5)\n#define\u0020_M_DRV_MCU_PORT_5_CR2\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_PORT_CR2+6)\n#define\u0020_M_DRV_MCU_PORT_6_CR2\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_PORT_CR2+7)\n\n#define\u0020_M_DRV_MCU_EXTI\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV+0x400)\n#define\u0020_M_DRV_MCU_EXTI_RST\u0020\u0020\u0020\u0020\u0020\u0020(0)\n#define\u0020_M_DRV_MCU_EXTI_INIT\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_EXTI+1)\n#define\u0020_M_DRV_MCU_EXTI_CHK\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_EXTI+2)\n\n//\u0020TIME\n#define\u0020_M_DRV_MCU_TIME\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV+0x300)\n#define\u0020_M_DRV_MCU_TIME_RST\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_TIME+1)\n#define\u0020_M_DRV_MCU_TIME_INIT\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_TIME+2)\n#define\u0020_M_DRV_MCU_TIME_CHK\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_TIME+3)\n#define\u0020_M_DRV_MCU_TIME_1\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_TIME+4)\n#define\u0020_M_DRV_MCU_TIME_2\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_TIME+5)\n#define\u0020_M_DRV_MCU_TIME_3\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_TIME+6)\n#define\u0020_M_DRV_MCU_TIME_4\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_TIME+7)\n#define\u0020_M_DRV_MCU_TIME_5\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_TIME+8)\n#define\u0020_M_DRV_MCU_TIME_6\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_TIME+9)\n#define\u0020_M_DRV_MCU_TIME_133US\u0020\u0020\u0020(0)//(_M_DRV_MCU_TIME+10)\n#define\u0020_M_DRV_MCU_TIME_166US\u0020\u0020(0)//(_M_DRV_MCU_TIME+11)\n#define\u0020_M_DRV_MCU_TIME_2MS\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_TIME+12)\n#define\u0020_M_DRV_MCU_TIME_10MS\u0020\u0020\u0020(0)//(_M_DRV_MCU_TIME+13)\n#define\u0020_M_DRV_MCU_TIME_1MS\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_TIME+14)\n#define\u0020_M_DRV_MCU_TIME_500US\u0020\u0020(_M_DRV_MCU_TIME+15)\n\n//\u0020AD\n#define\u0020_M_DRV_MCU_AD\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020\u0020(_M_DRV+0x500)\n#define\u0020_M_DRV_MCU_AD_RST\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_AD+1)\n#define\u0020_M_DRV_MCU_AD_INIT\u0020\u0020\u0020\u0020\u0020(_M_DRV_MCU_AD+2)\n#define\u0020_M_DRV_MCU_AD_CHK\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_AD+3)\n\n//\u0020CCP\n#define\u0020_M_DRV_MCU_CCP\u0020\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV+0x600)\n#define\u0020_M_DRV_MCU_CCP_RST\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_CCP+1)\n#define\u0020_M_DRV_MCU_CCP_INIT\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_CCP+2)\n#define\u0020_M_DRV_MCU_CCP_CHK\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_CCP+3)\n#define\u0020_M_DRV_MCU_CCP_PWM\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_CCP+4)\n#define\u0020_M_DRV_MCU_CCP_CAP\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_CCP+5)\n#define\u0020_M_DRV_MCU_TIME1_CCP_PWM\u0020(0)//(_M_DRV_MCU_CCP+6)\n#define\u0020_M_DRV_MCU_TIME2_CCP_PWM\u0020(0)//(_M_DRV_MCU_CCP+7)\n\n//\u0020SPI\n#define\u0020_M_DRV_MCU_SPI\u0020\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV+0x700)\n#define\u0020_M_DRV_MCU_SPI_RST\u0020\u0020\u0020\u0020\u0020(0)\n#define\u0020_M_DRV_MCU_SPI_INIT\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_SPI+2)\n#define\u0020_M_DRV_MCU_SPI_CHK\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU_SPI+3)\n\n//\u0020EEPROM\n#define\u0020_M_DRV_MCU_EEPROM\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV+0x800)\n#define\u0020_M_DRV_MCU_EEPROM_RST\u0020\u0020\u0020\u0020(0)//(_M_DRV+0x800)\n#define\u0020_M_DRV_MCU_EEPROM_INIT\u0020\u0020\u0020(0)//(_M_DRV+0x800)\n#define\u0020_M_DRV_MCU_EEPROM_CHK\u0020\u0020\u0020(0)//(_M_DRV+0x800)\n\n//\u0020UART\n#define\u0020_M_DRV_MCU_UART\u0020\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV+0xB00)\n#define\u0020_M_DRV_MCU_UART_RST\u0020\u0020\u0020\u0020\u0020(0)\n#define\u0020_M_DRV_MCU_UART_INIT\u0020\u0020\u0020\u0020(0)\n#define\u0020_M_DRV_MCU_UART_CHK\u0020\u0020\u0020\u0020\u0020(0)\n\n//\u0020AWU\n#define\u0020_M_DRV_MCU_AWU\u0020\u0020\u0020\u0020\u0020\u0020\u0020(0)//(_M_DRV_MCU\u0020+\u00200xE00)\n\n#endif