Verilog 6.144MHz 时钟生成器设计与测试

module clk_generator(\n input clk_in,\n output reg clk_out\n);\n\nreg [11:0] counter;\nwire clk_out_div;\n\nassign clk_out = clk_out_div;\n\n// Divide clk_in by 64 to generate 96kHz\nalways @(posedge clk_in) begin\n if (counter == 11'b11111111111) begin\n counter <= 12'b0;\n clk_out_div <= ~clk_out_div;\n end else begin\n counter <= counter + 1;\n end\nend\n\nendmodule\n\n// Testbench\nmodule clk_generator_tb;\n\nreg clk_in;\nwire clk_out;\n\nclk_generator dut(\n .clk_in(clk_in),\n .clk_out(clk_out)\n);\n\ninitial begin\n clk_in = 0;\n #5;\n clk_in = 1;\n #5;\n clk_in = 0;\n #5;\n clk_in = 1;\n #5;\n clk_in = 0;\n #5;\n clk_in = 1;\n #5;\n clk_in = 0;\n #5;\n clk_in = 1;\n #5;\n clk_in = 0;\n #5;\n clk_in = 1;\n #5;\n clk_in = 0;\n #5;\n $finish;\nend\n\nendmodule