VHDL 24进制计数器实现 - 代码解析与Verilog转换

{"title":"LIBRARY IEEE;--引用IEEE库\nUSE IEEE.STD_LOGIC_1164.ALL;--STD_LOGIC、STD_LOGIC_VECTOR数据类型在此程序包中，而且程序包\n--还包含此两种数据类型的逻辑运算。且IEEE库不属于VHDL标准库，必须予以声明\nUSE IEEE.STD_LOGIC_ARITH.ALL;--对STD_LOGIC类型的数据进行算术运算的程序包\nUSE IEEE.STD_LOGIC_UNSIGNED.ALL;--对STD_LOGIC_VECTOR数据类型进行无符号数运算需声明UNSIGNED，\n--如需进行有符号数运算，则需声明SIGNED\n\nENTITY COUNTER_24 IS\nPORT(\n\t\t\tCLK_1H,CLR: IN STD_LOGIC;--输入的计数脉冲\n\t\tHGEWEI,HSHIWEI:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));--输出个位及十位BCD码\nEND ENTITY COUNTER_24;\n\nARCHITECTURE RTL OF COUNTER_24 IS\nSIGNAL TMP1,TMP2:STD_LOGIC_VECTOR(3 DOWNTO 0);--引入信号TMP1、TMP2，存储计数器计数结果\nBEGIN\n\tPROCESS(CLK_1H)\n\tBEGIN\n\t\tIF(CLR='0')THEN--当清零控制管脚为低电平时，将中间信号量置零处理\n\t\t\tTMP1<="0000";TMP2<="0000";\n\t\tELSIF(CLK_1H'EVENT AND CLK_1H='1')THEN--当清零控制管脚为高电平时，判断输入计数脉冲有无上升沿到来\n\t\t\tIF(TMP2="0010" AND TMP1="0011")THEN--判断计数结果是否达到23\n\t\t\t\tTMP2<="0000";TMP1<="0000";--计数结果达到23，计数器清零\n\t\t\tELSIF(TMP1="1001")THEN--计数结果未达到23，但个位数计数结果为9\n\t\t\t\tTMP1<="0000";TMP2<=TMP2+1;--计数结果个位数清零，十位数进1\n\t\t\tELSE\n\t\t\t\tTMP1<=TMP1+1;--计数结果既未达到23，个位数计数结果也不为9，实现计数器个位数加1\n\t\t\tEND IF;\n\t\tEND IF;\n\tEND PROCESS;\n\tHGEWEI<=TMP1;HSHIWEI<=TMP2;--将计数器结果赋值给输出的个位数和十位数\nEND ARCHITECTURE RTL;\n将VHDR转换为verilog内容：library IEEE;\nuse IEEE.std_logic_1164.all;\nuse IEEE.std_logic_arith.all;\nuse IEEE.std_logic_unsigned.all;\n\nentity COUNTER_24 is\nport(\n CLK_1H, CLR: in std_logic;\n HGEWEI, HSHIWEI: out std_logic_vector(3 downto 0));\nend entity COUNTER_24;\n\narchitecture RTL of COUNTER_24 is\nsignal TMP1, TMP2: std_logic_vector(3 downto 0);\nbegin\n process(CLK_1H)\n begin\n if CLR = '0' then\n TMP1 <= "0000";\n TMP2 <= "0000";\n elsif rising_edge(CLK_1H) then\n if TMP2 = "0010" and TMP1 = "0011" then\n TMP2 <= "0000";\n TMP1 <= "0000";\n elsif TMP1 = "1001" then\n TMP1 <= "0000";\n TMP2 <= TMP2 + 1;\n else\n TMP1 <= TMP1 + 1;\n end if;\n end if;\n end process;\n \n HGEWEI <= TMP1;\n HSHIWEI <= TMP2;\nend architecture RTL;