Verilog 编译错误: `timescale` 语句缺少分号

`timescale 1ns/1ns\n\n`module top_module(output one);\n\t`assign one = 1; \n`endmodule; \n编译错误：\nmain.v:5: syntax error\nI give up. 内容：此处编译错误是因为`timescale`语句后面缺少一个分号。正确的代码应该是：\n\n`timescale 1ns/1ns`\n`module top_module(output one);`\n`assign one = 1; `\n`endmodule; `