FPGA 数字频率计模块化设计 - Verilog 实现

module frequency_counter( input clk, input rst, input signal, output [7:0] display );

reg [31:0] count; reg [31:0] freq;

always @(posedge clk or posedge rst) begin if (rst) begin count <= 0; freq <= 0; end else begin count <= count + 1; if (signal != signal_prev) begin freq <= count; count <= 0; end end end

assign display = freq[31:24];

endmodule