Verilog Key Debounce Module for Stable Input

This Verilog module implements a key debounce mechanism to filter out spurious key presses caused by mechanical contact bounce. It uses a 20ms counter to ensure a stable key state before registering the input.

module key_debounce(
  input            i_clk,
  input            i_rst_n,
  input      [9:1] i_key,               // 按下为0，松开为1
  output reg [9:1] o_key_val            // 键值
);

//++++++++++++++++++++++++++++++++++++++
reg [9:1] key_samp1, key_samp1_locked;

// 将i_key采集至key_samp1
always @ (posedge i_clk, negedge i_rst_n)
  if(!i_rst_n) 
    key_samp1 <= 9'h1FF;
  else         
    key_samp1 <= i_key;

// 将key_samp1锁存至key_samp1_locked
always @ (posedge i_clk, negedge i_rst_n)
  if(!i_rst_n) 
    key_samp1_locked <= 9'h1FF;
  else         
    key_samp1_locked <= key_samp1;
//--------------------------------------

//++++++++++++++++++++++++++++++++++++++
wire [9:1] key_changed1;

// 当key_samp1由1变为0时
// key_changed1由0变为1，只维持一个时钟周期
assign key_changed1 = key_samp1_locked & (~key_samp1); 
//--------------------------------------


//++++++++++++++++++++++++++++++++++++++
reg [19:0] cnt;

// 一旦有按键按下，cnt立即被清零
always @ (posedge i_clk, negedge i_rst_n)
  if(!i_rst_n)
    cnt <= 20'h0;
  else if(key_changed1)
    cnt <= 20'h0;
  else
    cnt <= cnt + 1'b1;
//--------------------------------------


//++++++++++++++++++++++++++++++++++++++
reg [9:1] key_samp2, key_samp2_locked;

// 只有当按键不变化（不抖动），且维持20ms以上时
// 才将i_key采集至key_samp2
always @ (posedge i_clk, negedge i_rst_n)
  if(!i_rst_n)
    key_samp2 <= 9'h1FF;
  else if(cnt == 20'hF_FFFF)            // 0xFFFFF/50M = 20.9715ms
    key_samp2 <= i_key;

// 将key_samp2锁存至key_samp2_locked
always @ (posedge i_clk, negedge i_rst_n)
  if(!i_rst_n)
    key_samp2_locked <= 9'h1FF;
  else
    key_samp2_locked <= key_samp2;
//--------------------------------------

//++++++++++++++++++++++++++++++++++++++
wire [9:1] key_changed2;

// 当key_samp2由1变为0时
// key_changed2由0变为1，只维持一个时钟周期
assign key_changed2 = key_samp2_locked & (~key_samp2); 
//--------------------------------------


  // 这一段程序的20MS怎么分出来的内容：程序中的20ms是通过计数器cnt实现的。每当有按键变化（由1变为0或由0变为1），计数器cnt会立即被清零。计数器cnt在每个时钟周期加1，因此当按键不变化时，cnt会一直增加，直到达到20ms。当cnt达到20ms时，程序会将当前按键状态采集到key_samp2中，从而消除按键抖动的影响，得到稳定的按键状态。
endmodule

Explanation

Key Sampling: The module captures the input key state (i_key) and stores it in key_samp1. This sample is then latched into key_samp1_locked on the next clock edge.
Change Detection: The key_changed1 signal detects when the key state changes from 1 to 0 by comparing the latched and current samples. This signal is only asserted for one clock cycle.
Debounce Counter: The cnt counter starts counting on each rising clock edge. It resets whenever a key change is detected.
Stable Key Capture: When cnt reaches 20'hF_FFFF, which corresponds to approximately 20ms at a 50MHz clock frequency, the key state is captured into key_samp2 if the key has not changed during that interval.
Output Value: The final stable key state is locked into key_samp2_locked and output as o_key_val.

This debounce scheme ensures that the output o_key_val only updates after the key state has been stable for at least 20ms, effectively eliminating the effects of contact bounce.

Usage

This module can be used in any digital circuit where key presses are used as input signals. The module is designed to be generic and can be easily modified to support different key configurations and clock frequencies.

Verilog Key Debounce Module for Stable Input