Verilog Key Debounce Module for Stable Key Press Detection

Verilog Key Debounce Module

This Verilog module implements a key debounce mechanism to ensure stable key press detection by filtering out mechanical switch bounce. The module utilizes a counter and two sampling stages to achieve a debounce delay of approximately 20 milliseconds.

module key_debounce(
  input            i_clk,
  input            i_rst_n,
  input      [9:1] i_key,               // 按下为0，松开为1
  output reg [9:1] o_key_val            // 键值
);

//++++++++++++++++++++++++++++++++++++++
reg [9:1] key_samp1, key_samp1_locked;

// 将i_key采集至key_samp1
always @ (posedge i_clk, negedge i_rst_n)
  if(!i_rst_n) 
    key_samp1 <= 9'h1FF;
  else         
    key_samp1 <= i_key;

// 将key_samp1锁存至key_samp1_locked
always @ (posedge i_clk, negedge i_rst_n)
  if(!i_rst_n) 
    key_samp1_locked <= 9'h1FF;
  else         
    key_samp1_locked <= key_samp1;
//--------------------------------------

//++++++++++++++++++++++++++++++++++++++
wire [9:1] key_changed1;

// 当key_samp1由1变为0时
// key_changed1由0变为1，只维持一个时钟周期
assign key_changed1 = key_samp1_locked & (~key_samp1); 
//--------------------------------------


//++++++++++++++++++++++++++++++++++++++
reg [19:0] cnt;

// 一旦有按键按下，cnt立即被清零
always @ (posedge i_clk, negedge i_rst_n)
  if(!i_rst_n)
    cnt <= 20'h0;
  else if(key_changed1)
    cnt <= 20'h0;
  else
    cnt <= cnt + 1'b1;
//--------------------------------------


//++++++++++++++++++++++++++++++++++++++
reg [9:1] key_samp2, key_samp2_locked;

// 只有当按键不变化（不抖动），且维持20ms以上时
// 才将i_key采集至key_samp2
always @ (posedge i_clk, negedge i_rst_n)
  if(!i_rst_n)
    key_samp2 <= 9'h1FF;
  else if(cnt == 20'hF_FFFF)            // 0xFFFFF/50M = 20.9715ms
    key_samp2 <= i_key;

// 将key_samp2锁存至key_samp2_locked
always @ (posedge i_clk, negedge i_rst_n)
  if(!i_rst_n)
    key_samp2_locked <= 9'h1FF;
  else
    key_samp2_locked <= key_samp2;
//--------------------------------------

//++++++++++++++++++++++++++++++++++++++
wire [9:1] key_changed2;

// 当key_samp2由1变为0时
// key_changed2由0变为1，只维持一个时钟周期
assign key_changed2 = key_samp2_locked & (~key_samp2); 
//--------------------------------------

endmodule

Explanation of the 20ms Debounce Delay

The 20ms debounce delay is achieved through the counter cnt. Here's how it works:

1. Counter Initialization: When the module is reset or a key press is detected (i.e., key_changed1 is high), the counter cnt is reset to 0.

2. Counting: In each clock cycle, cnt increments by 1.

3. Debounce Threshold: The counter cnt is compared against a threshold value of 20'hF_FFFF. This value represents 20,971 counts, which corresponds to approximately 20 milliseconds when the system clock is 50MHz.

4. Key Sampling: Only when cnt reaches the threshold value (20'hF_FFFF), is the current key state (i_key) sampled into key_samp2. This ensures that the sampled key state is relatively stable and not affected by switch bounce.

Therefore, the 20ms debounce delay is implemented by counting clock cycles until the counter reaches a specific threshold value. This approach effectively eliminates switch bounce by waiting for a stable key state before sampling the key input.

Conclusion

This Verilog module demonstrates a practical implementation of a key debounce mechanism to ensure accurate and stable key press detection. By utilizing a counter and a two-stage sampling approach, the module effectively filters out switch bounce and provides a reliable representation of the key state. This technique is commonly used in digital systems that rely on user input from mechanical buttons or switches.