Verilog实现110序列检测器：代码与测试

以下是Verilog代码，实现了一个110序列检测器：

module sequence_detector (
    input clk,
    input reset,
    input data,
    output reg out
);

reg [1:0] state;

parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;

always @(posedge clk, posedge reset) begin
    if (reset) begin
        state <= S0;
        out <= 0;
    end else begin
        case (state)
            S0: if (data == 1) state <= S1; else state <= S0;
            S1: if (data == 1) state <= S2; else state <= S0;
            S2: if (data == 0) begin state <= S0; out <= 1; end else state <= S2;
        endcase
    end
end

endmodule

以下是测试代码：

module sequence_detector_test;

reg clk;
reg reset;
reg data;
wire out;

sequence_detector detector (
    .clk(clk),
    .reset(reset),
    .data(data),
    .out(out)
);

initial begin
    clk = 0;
    reset = 1;
    data = 0;
    #10 reset = 0;
end

always #5 clk = ~clk;

initial begin
    $monitor('out=%b', out);
    #20 data = 1;
    #10 data = 1;
    #10 data = 0;
    #10 data = 1;
    #10 data = 1;
    #10 data = 1;
    #10 data = 0;
end

endmodule

在测试代码中，输入了11011010序列，输出结果应该为1010。