HDL 示例代码：组合逻辑、时序逻辑、状态机和 RTL 图

以下是 HDL 的组合逻辑、时序逻辑、状态机和 RTL 图示例代码：

组合逻辑示例代码：

module adder(a, b, c);
input [3:0] a, b;
output [3:0] c;
assign c = a + b;
endmodule

时序逻辑示例代码：

module counter(clk, reset, count);
input clk, reset;
output reg [3:0] count;
always @(posedge clk, posedge reset) begin
  if (reset)
    count <= 4'b0000;
  else
    count <= count + 1;
end
endmodule

状态机示例代码：

module traffic_light(clk, reset, light);
input clk, reset;
output reg [1:0] light;
parameter [1:0] RED = 2'b00, YELLOW = 2'b01, GREEN = 2'b10;
reg [1:0] state;

always @(posedge clk, posedge reset) begin
  if (reset)
    state <= RED;
  else begin
    case (state)
      RED: begin
        state <= GREEN;
        light <= GREEN;
      end
      GREEN: begin
        state <= YELLOW;
        light <= YELLOW;
      end
      YELLOW: begin
        state <= RED;
        light <= RED;
      end
    endcase
  end
end
endmodule

RTL 图示例代码：

module mux(input [3:0] a, b, sel, output [3:0] out);
assign out = (sel == 1'b0) ? a : b;
endmodule

以上代码仅供参考，具体实现方式可能因不同的需求而有所不同。