HDL 代码示例：组合逻辑、时序逻辑、状态机和 RTL 图

本文提供 Verilog HDL 代码示例，演示组合逻辑、时序逻辑、状态机和 RTL 图的实现方法。代码示例简单易懂，便于理解和学习 HDL 设计。

1. 组合逻辑代码示例

module adder(input [7:0] a, b, output [7:0] sum);

assign sum = a + b;

endmodule

2. 时序逻辑代码示例

module counter(input clk, input rst, output reg [3:0] count);

always @(posedge clk, posedge rst)
begin
    if (rst)
        count <= 4'b0;
    else
        count <= count + 1;
end

endmodule

3. 状态机代码示例

module fsm(input clk, input rst, input start, output reg done);

localparam S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;

reg [1:0] state;

always @(posedge clk, posedge rst)
begin
    if (rst)
        state <= S0;
    else
        case (state)
            S0: if (start)
                    state <= S1;
                else
                    state <= S0;
            S1: state <= S2;
            S2: state <= S0;
        endcase
end

assign done = (state == S0);

endmodule

4. RTL 图代码示例

module adder(input [7:0] a, b, output [7:0] sum);

assign sum = a + b;

endmodule

module counter(input clk, input rst, output reg [3:0] count);

always @(posedge clk, posedge rst)
begin
    if (rst)
        count <= 4'b0;
    else
        count <= count + 1;
end

endmodule

module fsm(input clk, input rst, input start, output reg done);

localparam S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;

reg [1:0] state;

always @(posedge clk, posedge rst)
begin
    if (rst)
        state <= S0;
    else
        case (state)
            S0: if (start)
                    state <= S1;
                else
                    state <= S0;
            S1: state <= S2;
            S2: state <= S0;
        endcase
end

assign done = (state == S0);

endmodule

module top(input clk, input rst, input start, input [7:0] a, b, output [7:0] sum, output reg done, output reg [3:0] count);

adder add_inst(.a(a), .b(b), .sum(sum));
counter count_inst(.clk(clk), .rst(rst), .count(count));
fsm fsm_inst(.clk(clk), .rst(rst), .start(start), .done(done));

endmodule

以上代码示例仅供参考，具体实现根据需要进行修改。