VHDL 实现 8 位序列计数器：连续零计数及错误检测

-- 定义模块 entity SequenceCounter is Port ( clk : in std_logic; reset : in std_logic; input : in std_logic_vector(7 downto 0); output : out std_logic_vector(3 downto 0); error : out std_logic); end SequenceCounter;

-- 实现模块 architecture Behavioral of SequenceCounter is signal count : integer range 0 to 8 := 0; -- 定义计数器，初始化为0 begin process (clk, reset) -- 处理时钟信号和复位信号 begin if reset = '1' then -- 复位信号为高电平时，计数器清零 count <= 0; output <= '0000'; error <= '0'; elsif rising_edge(clk) then -- 上升沿时进行计数 if input = '11111111' then -- 全1的序列为有效序列 count <= 0; output <= '0000'; error <= '0'; elsif input = '00000000' and count = 7 then -- 连续8个0为有效序列 count <= 8; output <= '1000'; error <= '0'; elsif input = '00000000' then -- 连续0未达到8个，计数器不变 count <= count; output <= '0000'; error <= '0'; else -- 非有效序列，计数器清零，错误指示信号输出高电平 count <= 0; output <= '0000'; error <= '1'; end if; end if; end process; end Behavioral;