Verilog 实现三乘六交换矩阵 - 代码和测试用例

以下是一个简单的三乘六的交换矩阵的 Verilog 代码和 testbench 代码：

module matrix_3x6(
    input [2:0] row,
    input [5:0] col,
    input [17:0] data_in,
    output [17:0] data_out
);

reg [17:0] matrix [0:2][0:5];

integer i, j;

always @(*) begin
    for (i = 0; i < 3; i = i + 1) begin
        for (j = 0; j < 6; j = j + 1) begin
            if (i == row && j == col) begin
                matrix[i][j] = data_in;
            end
        end
    end

    for (i = 0; i < 3; i = i + 1) begin
        for (j = 0; j < 6; j = j + 1) begin
            if (i == col && j == row) begin
                data_out = matrix[i][j];
            end
        end
    end
end

endmodule

module matrix_3x6_tb;

reg [2:0] row;
reg [5:0] col;
reg [17:0] data_in;
wire [17:0] data_out;

matrix_3x6 uut(
    .row(row),
    .col(col),
    .data_in(data_in),
    .data_out(data_out)
);

initial begin
    $monitor('Row: %d, Column: %d, Input Data: %d, Output Data: %d', row, col, data_in, data_out);

    // Test case 1: Swap row 1 and column 3
    row = 1;
    col = 3;
    data_in = 123;
    #10;

    // Test case 2: Swap row 2 and column 5
    row = 2;
    col = 5;
    data_in = 456;
    #10;

    // Test case 3: Swap row 0 and column 2
    row = 0;
    col = 2;
    data_in = 789;
    #10;

    // Test case 4: Swap row 1 and column 1
    row = 1;
    col = 1;
    data_in = 321;
    #10;

    // Test case 5: Swap row 2 and column 4
    row = 2;
    col = 4;
    data_in = 654;
    #10;

    // Test case 6: Swap row 0 and column 0
    row = 0;
    col = 0;
    data_in = 987;
    #10;

    $finish;
end

endmodule

这个交换矩阵可以通过 row 和 col 输入来选择要交换的行和列，并通过 data_in 输入来提供要交换的数据。输出 data_out 包含交换后的数据。

在 testbench 代码中，我们通过不同的输入值进行了六个测试用例，以测试交换矩阵的正确性。运行 testbench 时，我们可以看到每个测试用例的输入和输出数据。