RISC-V 32I CPU 顶层模块代码注释

// RISC-V 32I CPU 顶层模块 // 可以修改端口以进行调试 `include "tmp.v" // 包含了临时文件

module cpu( input wire clk_in, // 系统时钟信号 input wire rst_in, // 复位信号 input wire rdy_in, // 就绪信号，在低电平时暂停CPU

input  wire [ 7:0]          mem_din,		// 数据输入总线
output wire [ 7:0]          mem_dout,		// 数据输出总线
output wire [31:0]          mem_a,			// 地址总线（仅使用17:0）
output wire                 mem_wr,			// 写入/读取信号（1表示写入）

input  wire                 io_buffer_full, // 如果UART缓冲区已满为1

output wire [31:0]			dbgreg_dout		// CPU寄存器输出（调试演示）

);

wire rst = rst_in | (~rdy_in); // 重置信号为rst_in或者~rdy_in

wire if_stall; // 指令取出阶段暂停信号 wire id_stall; // 指令译码阶段暂停信号 wire mem_stall; // 存储器访问阶段暂停信号 wire [5:0] main_stall; // 主暂停信号 Stallctrl stallctrl( // 用于控制暂停的模块 .rst(rst_in), .if_stall(if_stall), .id_stall(id_stall), .mem_stall(mem_stall), .stall_out(main_stall) );

wire ex_out_branch_enable; // 执行阶段的分支使能信号 wire [31:0] ex_out_branch_addr; // 执行阶段分支的目标地址 wire [31:0] pc; // 程序计数器 Pc_Reg pc_reg( // 程序计数器模块 .clk(clk_in), .rst(rst), .pc(pc), .stall(main_stall), .branch_enable(ex_out_branch_enable), .branch_addr(ex_out_branch_addr) );

wire wb_rd_enable; // 写回阶段寄存器写使能信号 wire [31:0] wb_rd_num; // 写回阶段寄存器写入的数据 wire [4:0] wb_rd_addr; // 写回阶段寄存器的地址 // wire write_enable; // wire [4:0] write_addr; // wire [31:0] write_data;

wire reg1_read_enable; // 第一个寄存器的读使能信号 wire [4:0] reg1_addr; // 第一个寄存器的地址 wire [31:0] reg1_data; // 第一个寄存器的数据 wire reg2_read_enable; // 第二个寄存器的读使能信号 wire [4:0] reg2_addr; // 第二个寄存器的地址 wire [31:0] reg2_data; // 第二个寄存器的数据 Register register( // 寄存器模块 .clk(clk_in), .rst(rst), .write_enable(wb_rd_enable), .write_addr(wb_rd_addr), .write_data(wb_rd_num), .reg1_read_enable(reg1_read_enable),
.reg1_addr(reg1_addr), .reg1_data(reg1_data), .reg2_read_enable(reg2_read_enable),
.reg2_addr(reg2_addr), .reg2_data(reg2_data) );

wire [31:0] if_to_ifid_pc; // 指令取出阶段到指令译码阶段的程序计数器值 wire [31:0] if_inst; // 指令取出阶段的指令 wire if_to_mem_ctrl_enable; // 指令取出阶段到存储控制器的使能信号 wire [31:0] if_to_mem_ctrl_addr; // 指令取出阶段到存储控制器的地址 wire mem_ctrl_to_if_busy; // 存储控制器到指令取出阶段的忙信号 wire mem_ctrl_to_if_enable; // 存储控制器到指令取出阶段的使能信号 wire [31:0] mem_ctrl_to_if_inst; // 存储控制器到指令取出阶段的指令 wire mem_ctrl_to_mem_busy; // 存储控制器到存储器的忙信号 wire mem_ctrl_to_mem_enable; // 存储控制器到存储器的使能信号 IF ifif( // 指令取出阶段模块 .rst(rst), .pc_in(pc), .mem_ctrl_inst_in(mem_ctrl_to_if_inst), .mem_ctrl_busy_if_in(mem_ctrl_to_if_busy), .mem_ctrl_busy_mem_in(mem_ctrl_to_mem_busy), .mem_ctrl_inst_done_in(mem_ctrl_to_if_enable), // .mem_ctrl_mem_done_in(mem_ctrl_to_mem_enable), .branch_enable(ex_out_branch_enable), .mem_ctrl_enable_out(if_to_mem_ctrl_enable), .mem_ctrl_addr_out(if_to_mem_ctrl_addr), .stall_from_if(if_stall), .pc_out(if_to_ifid_pc), .inst_out(if_inst) );

wire [31:0] ifid_to_id_pc; // 指令取出阶段到指令译码阶段的程序计数器值 wire [31:0] id_inst; // 指令译码阶段的指令 IFID ifid( // 指令译码阶段模块 .clk(clk_in), .rst(rst), .stall(main_stall), .if_pc(if_to_ifid_pc), .if_inst(if_inst), .id_pc(ifid_to_id_pc), .id_inst(id_inst), .branch_enable(ex_out_branch_enable) );

wire [31:0] id_rs1; // 指令译码阶段的第一个寄存器值 wire [31:0] id_rs2; wire [31:0] id_imm; // 指令译码阶段的立即数 wire [4:0] id_rd_addr; // 指令译码阶段的目的寄存器地址 wire id_rd_enable; // 指令译码阶段的目的寄存器写使能信号 wire [5:0] id_aluop; // 指令译码阶段的ALU操作码 wire [2:0] id_alusel; // 指令译码阶段的ALU选择信号 wire [31:0] id_to_idex_pc; // 指令译码阶段到执行阶段的程序计数器值 ID id( .rst(rst), .pc_in(ifid_to_id_pc), .pc_out(id_to_idex_pc), .inst(id_inst), .reg1_read_enable(reg1_read_enable),
.reg1_addr(reg1_addr), .reg1_data(reg1_data), .reg2_read_enable(reg2_read_enable),
.reg2_addr(reg2_addr), .reg2_data(reg2_data), .rs1_num(id_rs1), .rs2_num(id_rs2), .imm(id_imm), .rd(id_rd_addr), .rd_enable(id_rd_enable), .aluop(id_aluop), .alusel(id_alusel) );

wire [31:0] ex_rs1; // 执行阶段的第一个寄存器值 wire [31:0] ex_rs2; // 执行阶段的第二个寄存器值 wire [31:0] ex_imm; // 执行阶段的立即数 wire [4:0] idex_to_ex_rd_addr; // 指令译码/执行阶段到执行阶段的目的寄存器地址 wire [31:0] idex_to_ex_pc; // 指令译码/执行阶段到执行阶段的程序计数器值 wire idex_to_ex_rd_enable; // 指令译码/执行阶段到执行阶段的目的寄存器写使能信号 wire [5:0] ex_aluop; // 执行阶段的ALU操作码 wire [2:0] ex_alusel; // 执行阶段的ALU选择信号 IDEX idex( .clk(clk_in), .rst(rst), .stall(main_stall), .id_rs1(id_rs1), .id_rs2(id_rs2), .id_imm(id_imm), .id_rd_addr(id_rd_addr), .id_rd_enable(id_rd_enable), .id_aluop(id_aluop), .id_alusel(id_alusel), .id_pc(id_to_idex_pc), .ex_rs1(ex_rs1), .ex_rs2(ex_rs2), .ex_imm(ex_imm), .ex_rd_addr(idex_to_ex_rd_addr), .ex_rd_enable(idex_to_ex_rd_enable), .ex_aluop(ex_aluop), .ex_alusel(ex_alusel), .ex_pc(idex_to_ex_pc), .branch_enable(ex_out_branch_enable) );

wire [31:0] ex_rd_num; // 执行阶段的目的寄存器写入数据 wire [4:0] ex_rd_addr; // 执行阶段的目的寄存器地址 wire ex_rd_enable; // 执行阶段的目的寄存器写使能信号 wire [31:0] ex_val_store_num; // 执行阶段存储数据 wire [31:0] ex_val_store_and_load_addr; // 执行阶段存储/加载地址 wire ex_val_store_enable; // 执行阶段存储使能信号 wire ex_val_load_enable; // 执行阶段加载使能信号 EX ex( .rst(rst), .rs1(ex_rs1), .rs2(ex_rs2), .imm(ex_imm), .rd_addr_in(idex_to_ex_rd_addr), .rd_enable_in(idex_to_ex_rd_enable), .aluop(ex_aluop), .alusel(ex_alusel), .pc_in(idex_to_ex_pc), .pc_change(ex_out_branch_enable), .new_pc_num(ex_out_branch_addr), .rd_num_out(ex_rd_num), .rd_addr_out(ex_rd_addr), .rd_enable_out(ex_rd_enable), .val_store_num(ex_val_store_num), .val_store_and_load_addr(ex_val_store_and_load_addr), .val_store_enable(ex_val_store_enable), .val_load_enable(ex_val_load_enable) );

wire exmem_to_mem_rd_enable; // 执行/存储器访问阶段到存储器访问阶段的目的寄存器写使能信号 wire [31:0] exmem_to_mem_rd_num; // 执行/存储器访问阶段到存储器访问阶段的目的寄存器写入数据 wire [4:0] exmem_to_mem_rd_addr; // 执行/存储器访问阶段到存储器访问阶段的目的寄存器地址 wire [5:0] mem_aluop; // 存储器访问阶段的ALU操作码 wire [31:0] mem_val_store_num; // 存储器访问阶段存储数据 wire [31:0] mem_val_store_and_load_addr; // 存储器访问阶段存储/加载地址 wire mem_val_store_enable; // 存储器访问阶段存储使能信号 wire mem_val_load_enable; // 存储器访问阶段加载使能信号 EXMEM exmem( .clk(clk_in), .rst(rst), .stall(main_stall), .ex_rd_enable(ex_rd_enable), .ex_rd_num(ex_rd_num), .ex_rd_addr(ex_rd_addr), .ex_aluop(ex_aluop), .ex_val_store_num(ex_val_store_num), .ex_val_store_and_load_addr(ex_val_store_and_load_addr), .ex_val_store_enable(ex_val_store_enable), .ex_val_load_enable(ex_val_load_enable), .mem_rd_enable(exmem_to_mem_rd_enable), .mem_rd_num(exmem_to_mem_rd_num), .mem_rd_addr(exmem_to_mem_rd_addr), .mem_aluop(mem_aluop), .mem_val_store_num(mem_val_store_num), .mem_val_store_and_load_addr(mem_val_store_and_load_addr), .mem_val_store_enable(mem_val_store_enable), .mem_val_load_enable(mem_val_load_enable) );

wire mem_rd_enable; // 存储器访问阶段的目的寄存器写使能信号 wire [31:0] mem_rd_num; // 存储器访问阶段的目的寄存器写入数据 wire [4:0] mem_rd_addr; // 存储器访问阶段的目的寄存器地址 // wire mem_ctrl_to_mem_enable; wire [31:0] mem_ctrl_to_mem_addr; // 存储控制器到存储器的地址 wire [31:0] mem_ctrl_to_mem_data; // 存储控制器到存储器的数据 wire mem_to_mem_ctrl_enable; // 存储器到存储控制器的使能信号 wire mem_to_mem_ctrl_rw_status; // 存储器到存储控制器的读写状态 wire [31:0] mem_to_mem_ctrl_addr; // 存储器到存储控制器的地址 wire [31:0] mem_to_mem_ctrl_data; // 存储器到存储控制器的写入数据 wire [2:0] mem_to_mem_ctrl_data_len; // 存储器到存储控制器的写入数据长度 MEM mem( .rst(rst), .rd_enable_in(exmem_to_mem_rd_enable), .rd_addr_in(exmem_to_mem_rd_addr), .rd_num_in(exmem_to_mem_rd_num), .aluop(mem_aluop), .val_store_num(mem_val_store_num), .val_store_and_load_addr(mem_val_store_and_load_addr), .val_store_enable(mem_val_store_enable), .val_load_enable(mem_val_load_enable), .mem_ctrl_enable_in(mem_ctrl_to_mem_enable), .mem_ctrl_if_busy_in(mem_ctrl_to_if_busy), .mem_ctrl_mem_busy_in(mem_ctrl_to_mem_busy), .mem_ctrl_addr_in(mem_ctrl_to_mem_addr), .mem_ctrl_data_in(mem_ctrl_to_mem_data), .mem_ctrl_enable_out(mem_to_mem_ctrl_enable), .mem_ctrl_rw_status_out(mem_to_mem_ctrl_rw_status), .mem_ctrl_addr_out(mem_to_mem_ctrl_addr), .mem_ctrl_data_out(mem_to_mem_ctrl_data), .mem_ctrl_data_len_out(mem_to_mem_ctrl_data_len), .stall_from_mem(mem_stall), .rd_enable_out(mem_rd_enable), .rd_data_out(mem_rd_num), .rd_addr_out(mem_rd_addr) );

MEMCTRL memctrl( .clk(clk_in), .rst(rst), .if_enable_in(if_to_mem_ctrl_enable), .if_addr_in(if_to_mem_ctrl_addr), .mem_enable_in(mem_to_mem_ctrl_enable), .mem_rw_status_in(mem_to_mem_ctrl_rw_status), .mem_addr_in(mem_to_mem_ctrl_addr), .mem_data_in(mem_to_mem_ctrl_data), .mem_data_len_in(mem_to_mem_ctrl_data_len), .ram_data_in(mem_din), .ram_rw_status_out(mem_wr), .ram_addr_out(mem_a), .ram_data_out(mem_dout), .if_busy_out(mem_ctrl_to_if_busy), .if_enable_out(mem_ctrl_to_if_enable), .if_inst_out(mem_ctrl_to_if_inst), .mem_busy_out(mem_ctrl_to_mem_busy), .mem_enable_out(mem_ctrl_to_mem_enable), .mem_data_out(mem_ctrl_to_mem_data) );

MEMWB memwb( .clk(clk_in), .rst(rst), .stall(main_stall), .mem_rd_enable(mem_rd_enable), .mem_rd_num(mem_rd_num), .mem_rd_addr(mem_rd_addr), .wb_rd_enable(wb_rd_enable), .wb_rd_num(wb_rd_num), .wb_rd_addr(wb_rd_addr) ); endmodule