流水线寄存器 ExMem 模块：保存执行结果并控制下一个阶段

// 定义流水线寄存器 ExMem，用于保存执行结果并控制下一个阶段是否写入存储器和寄存器 module ExMem(clk,run,jump,ALUSrc,MemWr,Branch,MemtoReg,RegWr,busB,rw, addr,pc3,ALUout,zero,overflow,outMemWr,outBranch,outMemtoReg,outRegWr, outBusB,outRw,outAddr,outpc3,outALUout,outZero,outOverflow,outALUSrc,outJump); // 输入时钟和跳转信号 input clk,jump; // 输入启动信号 input run; // 输入存储器写入、分支、寄存器、寄存器写入、零、溢出、ALU源信号 input MemWr,Branch,MemtoReg,RegWr,zero,overflow,ALUSrc; // 输入总线、地址、PC计数、ALU输出信号 input[31:0] busB,addr,pc3,ALUout; // 输入写信号 input[4:0] rw; // 传递给下阶段的信号 output outMemWr,outBranch,outMemtoReg,outRegWr,outZero,outOverflow,outALUSrc,outJump; output[31:0] outBusB,outAddr,outpc3,outALUout; output[4:0] outRw; // 声明输出信号的寄存器 reg outMemWr,outBranch,outMemtoReg,outRegWr,outZero,outOverflow,outALUSrc,outJump; reg[31:0] outBusB,outAddr,outpc3,outALUout; reg[4:0] outRw; // 时钟下降沿触发 always @(negedge clk) // 如果有启动信号，则输出信号从寄存器中取出并赋值给对应的输出信号 if(run==1) begin outMemWr<=MemWr; outBranch<=Branch; outMemtoReg<=MemtoReg; outRegWr<=RegWr; outZero<=zero; outOverflow<=overflow; outBusB<=busB; outAddr<=addr; outpc3<=pc3; outRw<=rw; outALUout<=ALUout; outALUSrc<=ALUSrc; outJump<=jump; end else // 如果没有启动信号，则将输出信号清零 begin outMemWr<=0; outBranch<=0; outMemtoReg<=0; outRegWr<=0; outZero<=0; outOverflow<=0; outBusB<=0; outAddr<=0; outpc3<=0; outRw<=0; outALUout<=0; outALUSrc<=0; outJump<=0; end endmodule

// 以下为各个模块的实例化及其连接，具体代码未给出，注释中只做简单说明

// 执行模块 Exec exec(pc2,outTarget,outBusA,outBusB,outImm16,outFunc,outRt,outRd,outALUout,result,outRegDst,outExtOP,outALUSrc, outALUCtrl,outRegWr2,rw2,outRw,outRegWr,outRs,outRt,addr,pc3,ALUout,zero,overflow,rw,A,B,ALUSrcA,ALUSrcB);

// 流水线寄存器 ExMem 模块 ExMem exMem(clk,run,outjump,outALUSrc,outMemWr,outBranch,outMemtoReg,outRegWr,outBusB,rw,addr,pc3,ALUout,zero,overflow, MemWr2,Branch2,MemtoReg2,RegWr2,busB2,outRw,outAddr,outpc3,outALUout,outZero,outOverflow,ALUSrc2,jump2);

// 存储器模块 Mem mem(clk,outALUout,MemWr2,busB2,DataOut);

// 存储器写入模块 MemWr mem_Wr(clk,run,MemtoReg2,RegWr2,DataOut,outOverflow,outRw,outALUout,outMemtoReg2,outRegWr2,outDataout,overflow2,rw2, ALUout2);

// 写入模块 Write write(outDataout,ALUout2,outMemtoReg2,result);

endmodule