Low-Power PUF Design for IoT Applications: Circuit Structure, Modeling, and Chip Testing

In addition, each amplifier unit in the PUF circuit has a choke tube, which results in very low power consumption, making it particularly suitable for terminal applications in the Internet of Things. The PUF circuit structure and nonlinear mathematical model proposed in this paper will be described in sections II and III, respectively. Section IV presents the test results of the designed chip, which was manufactured using the 65nm standard CMOS process. Finally, section V provides a summary of this paper.