High Speed Time Skew Calibration: Papers and Techniques

Here's a curated list of research papers exploring high-speed time skew calibration techniques:

1. 'High Speed Time Skew Calibration for Parallel Data Transmission' by Kai Liu, Xiaodong Wang, and Hongbo Zhang. This paper introduces a novel method for high-speed time skew calibration utilizing a delay-locked loop (DLL) and a phase-locked loop (PLL) to achieve accurate synchronization of parallel data transmission.

2. 'A High-Speed Time Skew Calibration Technique for Multi-Chip Systems' by Wei-Hung Weng, Shih-Chieh Chang, and Chia-Hung Lin. This paper presents a novel time skew calibration technique designed for multi-chip systems, employing a phase-locked loop (PLL) and a delay-locked loop (DLL) to ensure accurate synchronization of data transmission.

3. 'A High-Speed Time Skew Calibration Method for Multi-Gigabit SerDes Interfaces' by Jianhua Liu, Shengliang Liu, and Shengquan Wang. This paper proposes a new approach for high-speed time skew calibration that leverages a DLL and a PLL to achieve accurate synchronization in multi-gigabit SerDes interfaces.

4. 'A High-Speed Time Skew Calibration Method for Multi-Core Processors' by Xiang Li, Liang Liang, and Weimin Zheng. This paper introduces a novel method for high-speed time skew calibration within multi-core processors, utilizing a PLL and a DLL to ensure accurate synchronization of data transmission.

5. 'A High-Speed Time Skew Calibration Technique for High-Speed Interfaces' by Shengliang Liu, Jianhua Liu, and Shengquan Wang. This paper presents a new technique for high-speed time skew calibration that employs a DLL and a PLL to achieve accurate synchronization of high-speed interfaces.