使用verilog生成一个6144Mhz的时钟

module clk_generator( input clk_in, output reg clk_out );

reg [11:0] counter; wire clk_out_div;

assign clk_out = clk_out_div;

// Divide clk_in by 64 to generate 96kHz always @(posedge clk_in) begin if (counter == 11'b11111111111) begin counter <= 12'b0; clk_out_div <= ~clk_out_div; end else begin counter <= counter + 1; end end

endmodule

// Testbench module clk_generator_tb;

reg clk_in; wire clk_out;

clk_generator dut( .clk_in(clk_in), .clk_out(clk_out) );

initial begin clk_in = 0; #5; clk_in = 1; #5; clk_in = 0; #5; clk_in = 1; #5; clk_in = 0; #5; clk_in = 1; #5; clk_in = 0; #5; clk_in = 1; #5; clk_in = 0; #5; clk_in = 1; #5; clk_in = 0; #5; $finish; end

endmodul