LIBRARY IEEE;--引用IEEE库USE IEEESTD_LOGIC_1164ALL;--STD_LOGIC数据类型定义在此程序包中USE IEEESTD_LOGIC_ARITHALL;--该程序包定义了一些不同类型数据之间相互转化的函数USE IEEESTD_LOGIC_UNSIGNEDALL;--该程序包定义了与unsigned数据类型相关的函数ENTITY ymxsdl_1 IS-

module ymxsdl_1 ( XY, TEST, ZXY, D, C, B, A, Y );

input XY; input TEST; input ZXY; input D; input C; input B; input A; output reg [6:0] Y;

reg [3:0] TMP; reg [6:0] TEMP;

always @(XY or TEST or ZXY or D or C or B or A) begin if(XY == 0) begin TEMP <= 7'b1111111; end else if(TEST == 0) begin TEMP <= 7'b0000000; end else if(TMP == 4'b0000) begin if(ZXY == 0) begin TEMP <= 7'b1111111; end else begin TEMP <= 7'b0000001; end end else if(TMP == 4'b0001) begin TEMP <= 7'b1001111; end else if(TMP == 4'b0010) begin TEMP <= 7'b0010010; end else if(TMP == 4'b0011) begin TEMP <= 7'b0000110; end else if(TMP == 4'b0100) begin TEMP <= 7'b1001100; end else if(TMP == 4'b0101) begin TEMP <= 7'b0100100; end else if(TMP == 4'b0110) begin TEMP <= 7'b0100000; end else if(TMP == 4'b0111) begin TEMP <= 7'b0001111; end else if(TMP == 4'b1000) begin TEMP <= 7'b0000000; end else if(TMP == 4'b1001) begin TEMP <= 7'b0000100; end else if(TMP == 4'b1010) begin TEMP <= 7'b0001000; end else if(TMP == 4'b1011) begin TEMP <= 7'b1100000; end else if(TMP == 4'b1100) begin TEMP <= 7'b0110001; end else if(TMP == 4'b1101) begin TEMP <= 7'b1000010; end else if(TMP == 4'b1110) begin TEMP <= 7'b0110000; end else if(TMP == 4'b1111) begin TEMP <= 7'b0111000; end end

assign Y = TEMP;

endmodul