Verilog 中wire 30 mem_write_enable; rd_en = ~mem_write_enable0 & ~mem_write_enable1 & ~mem_write_enable2 & ~mem_write_enable3化简后是什么
化简后的表达式是：
rd_en = ~(mem_write_enable[0] | mem_write_enable[1] | mem_write_enable[2] | mem_write_enable[3])
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