给出使用vhdl设计时钟的代码要求时分秒显示在数码管输入时钟为10KHz

entity clock is port( clk_in : in std_logic; reset : in std_logic; seg_out : out std_logic_vector(6 downto 0); anode : out std_logic_vector(3 downto 0) ); end clock;

architecture Behavioral of clock is signal sec : integer range 0 to 59 := 0; signal min : integer range 0 to 59 := 0; signal hour : integer range 0 to 23 := 0; signal count : integer range 0 to 9999 := 0; signal digit : integer range 0 to 3 := 0; signal seg : std_logic_vector(6 downto 0) := "0000000"; signal an : std_logic_vector(3 downto 0) := "1110";

begin

process(clk_in, reset)
begin
    if reset = '1' then
        sec <= 0;
        min <= 0;
        hour <= 0;
        count <= 0;
        digit <= 0;
        seg <= "0000000";
        an <= "1110";
    elsif rising_edge(clk_in) then
        count <= count + 1;
        if count = 10000 then
            count <= 0;
            sec <= sec + 1;
            if sec = 60 then
                sec <= 0;
                min <= min + 1;
                if min = 60 then
                    min <= 0;
                    hour <= hour + 1;
                    if hour = 24 then
                        hour <= 0;
                    end if;
                end if;
            end if;
        end if;
    end if;
end process;

process(sec, min, hour)
begin
    case digit is
        when 0 => seg <= conv_std_logic_vector(hour/10, 7);
                  an <= "1110";
        when 1 => seg <= conv_std_logic_vector(hour mod 10, 7);
                  an <= "1101";
        when 2 => seg <= conv_std_logic_vector(min/10, 7);
                  an <= "1011";
        when 3 => seg <= conv_std_logic_vector(min mod 10, 7);
                  an <= "0111";
        when others => seg <= "0000000";
    end case;
end process;

seg_out <= seg;
anode <= an;

end Behavioral