把这段摘要翻译成英文随着微电子技术的不断发展集成电路器件已经成为现代电子技术中不可或缺的主要组成部分在器件尺寸不断缩小的必然趋势下MOS器件的可靠性要求也越来越高。深亚微米尺寸MOS器件的可靠性问题主要包括负偏置温度不稳定性效应热载流子注入效应栅氧化层经时击穿效应等。这些效应导致MOS器件发生阈值电压增大漏饱和电流减小跨导偏移等退化因此对MOS器件的失效机理进行仿真研究具有重要意义。本文针对PMO

With the continuous development of microelectronic technology, integrated circuit devices have become an indispensable part of modern electronic technology. As the size of devices continues to shrink, the reliability requirements of MOS devices are becoming increasingly higher. The reliability issues of MOS devices in deep submicron size mainly include negative bias temperature instability (NBTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB) of the gate oxide layer. These effects lead to degradation such as threshold voltage increase, decrease in saturation current, and transconductance shift. Therefore, simulating the failure mechanism of MOS devices is of great significance.

In this paper, a simulation model of threshold voltage degradation of PMOS transistor under coupled failure effects is proposed based on a unified reaction-diffusion theory framework for NBTI and HCI effects. The main research contents and results are as follows: A simulation model of threshold voltage degradation of MOS transistor under the individual NBTI, HCI effects, and coupled effects is constructed using the sde module of Sentaurus TCAD, and the sdevice module is used for simulation analysis of the specific mobility characteristics and threshold voltage degradation. The research results show that under the same voltage stress of 1.2V and a stress time of 1000s, the threshold voltage degradation rate caused by HCI effect is about 6 times that of NBTI effect. Under the voltage stress of 1.2V and a stress time of 1000s, the threshold voltage degradation caused by NBTI and coupled failure is 7.42% and 9.70%, respectively, indicating that the threshold voltage of MOS devices will be further aggravated under the combined effects of these two factors