利用VHDL编写一个八位寄存器

entity register is port( data_in : in std_logic_vector(7 downto 0); clk : in std_logic; enable : in std_logic; reset : in std_logic; data_out : out std_logic_vector(7 downto 0) ); end register;

architecture Behavioral of register is begin process(clk, reset) begin if reset = '1' then data_out <= (others => '0'); elsif rising_edge(clk) then if enable = '1' then data_out <= data_in; end if; end if; end process; end Behavioral