请在下面添加代码基于上面给出的的8位加法器和其它必要的逻辑门完成8位算术逻辑单元ALU的建模module alu_8bits input 7 0 A input 7 0 B input 3 0 aluop output 7 0 alu_res output ZF output SF output

wire [7:0] add_res; wire [7:0] sub_res; wire [7:0] and_res; wire [7:0] or_res; wire [7:0] xor_res; wire [7:0] not_a; wire [7:0] not_b;

assign not_a = ~A; assign not_b = ~B;

// Adder full_adder_1bit fa0(.a(A[0]), .b(B[0]), .c(1'b0), .s(add_res[0]), .c_out(CF)); full_adder_1bit fa1(.a(A[1]), .b(B[1]), .c(CF), .s(add_res[1]), .c_out(CF)); full_adder_1bit fa2(.a(A[2]), .b(B[2]), .c(CF), .s(add_res[2]), .c_out(CF)); full_adder_1bit fa3(.a(A[3]), .b(B[3]), .c(CF), .s(add_res[3]), .c_out(CF)); full_adder_1bit fa4(.a(A[4]), .b(B[4]), .c(CF), .s(add_res[4]), .c_out(CF)); full_adder_1bit fa5(.a(A[5]), .b(B[5]), .c(CF), .s(add_res[5]), .c_out(CF)); full_adder_1bit fa6(.a(A[6]), .b(B[6]), .c(CF), .s(add_res[6]), .c_out(CF)); full_adder_1bit fa7(.a(A[7]), .b(B[7]), .c(CF), .s(add_res[7]), .c_out(OF));

// Subtractor full_adder_1bit fa0_sub(.a(A[0]), .b(not_b[0]), .c(1'b1), .s(sub_res[0]), .c_out(CF)); full_adder_1bit fa1_sub(.a(A[1]), .b(not_b[1]), .c(CF), .s(sub_res[1]), .c_out(CF)); full_adder_1bit fa2_sub(.a(A[2]), .b(not_b[2]), .c(CF), .s(sub_res[2]), .c_out(CF)); full_adder_1bit fa3_sub(.a(A[3]), .b(not_b[3]), .c(CF), .s(sub_res[3]), .c_out(CF)); full_adder_1bit fa4_sub(.a(A[4]), .b(not_b[4]), .c(CF), .s(sub_res[4]), .c_out(CF)); full_adder_1bit fa5_sub(.a(A[5]), .b(not_b[5]), .c(CF), .s(sub_res[5]), .c_out(CF)); full_adder_1bit fa6_sub(.a(A[6]), .b(not_b[6]), .c(CF), .s(sub_res[6]), .c_out(CF)); full_adder_1bit fa7_sub(.a(A[7]), .b(not_b[7]), .c(CF), .s(sub_res[7]), .c_out(OF));

// AND, OR, XOR assign and_res = A & B; assign or_res = A | B; assign xor_res = A ^ B;

// ALU logic always @(*) begin case(aluop) 4'b0000: alu_res = add_res; // Addition 4'b0001: alu_res = sub_res; // Subtraction 4'b0010: alu_res = and_res; // Bitwise AND 4'b0011: alu_res = or_res; // Bitwise OR 4'b0100: alu_res = xor_res; // Bitwise XOR 4'b0101: alu_res = A; // Pass A 4'b0110: alu_res = B; // Pass B 4'b0111: alu_res = not_a; // Bitwise NOT A 4'b1000: alu_res = not_b; // Bitwise NOT B default: alu_res = 8'h00; // Default to 0 endcase end

// Zero flag assign ZF = (alu_res == 0);

// Sign flag assign SF = (alu_res[7] == 1);

endmodul