利用VHDL语言编写一个八位寄存器

entity eight_bit_register is port ( clk : in std_logic; rst : in std_logic; din : in std_logic_vector(7 downto 0); load : in std_logic; dout : out std_logic_vector(7 downto 0) ); end eight_bit_register;

architecture Behavioral of eight_bit_register is signal reg : std_logic_vector(7 downto 0);

begin process (clk, rst) begin if rst = '1' then reg <= (others => '0'); elsif rising_edge(clk) then if load = '1' then reg <= din; end if; end if; end process;

dout <= reg;

end Behavioral