写一个Verilog代码实现以下功能每一秒计数加1并且LED灯闪一次计数要求用7段数码管动态显示并且要求可以显示到100同时请写出对应的激励代码

Verilog代码：

module counter(
    input clk,
    output reg [6:0] seg,
    output reg [3:0] anode,
    output reg led
);

reg [6:0] count;
reg [3:0] digit;
reg [23:0] timer;

always @(posedge clk) begin
    if (timer == 24000000) begin // 1秒钟
        timer <= 0;
        count <= count + 1;
        led <= ~led;
        if (count > 99) begin
            count <= 0;
        end
    end else begin
        timer <= timer + 1;
    end
end

always @(posedge clk) begin
    case(digit)
        0: seg <= 7'b1000000; // 0
        1: seg <= 7'b1111001; // 1
        2: seg <= 7'b0100100; // 2
        3: seg <= 7'b0110000; // 3
        4: seg <= 7'b0011001; // 4
        5: seg <= 7'b0010010; // 5
        6: seg <= 7'b0000010; // 6
        7: seg <= 7'b1111000; // 7
        8: seg <= 7'b0000000; // 8
        9: seg <= 7'b0010000; // 9
        10: seg <= 7'b0001000; // A
        11: seg <= 7'b0000011; // b
        12: seg <= 7'b0100111; // C
        13: seg <= 7'b0100001; // d
        14: seg <= 7'b0000110; // E
        15: seg <= 7'b0001110; // F
        default: seg <= 7'b0000000;
    endcase
end

always @(posedge clk) begin
    case(digit)
        0: anode <= 4'b1110; // 第一个数码管
        1: anode <= 4'b1101; // 第二个数码管
        2: anode <= 4'b1011; // 第三个数码管
        default: anode <= 4'b1111;
    endcase
    
    digit <= digit + 1;
    if (digit == 3) begin
        digit <= 0;
    end
end

endmodule

激励代码：

module counter_tb;

reg clk;
wire [6:0] seg;
wire [3:0] anode;
wire led;

counter uut(
    .clk(clk),
    .seg(seg),
    .anode(anode),
    .led(led)
);

initial begin
    clk <= 0;
    #5;
    forever #10 clk = ~clk;
end

endmodule
``