VHDL 8-bit Adder with Carry-in and Carry-out

This VHDL code implements an 8-bit adder with carry-in and carry-out signals. The code demonstrates the basic operations of addition and carry propagation in VHDL.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164;

ENTITY ADD8bit IS
PORT(A, B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     Cin: IN STD_LOGIC;
     Y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     Cout: OUT STD_LOGIC);
END ADD8bit;

ARCHITECTURE ONE OF ADD8bit IS
	SIGNAL AA, BB, temp: STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
	AA <= '0' & A;
	BB <= '0' & B;
	temp <= AA + BB + Cin;
	Y <= temp(7 DOWNTO 0);
	Cout <= temp(8);
END ONE;

Explanation:

LIBRARY IEEE: Specifies the use of the IEEE library, which provides standard VHDL packages.
USE IEEE.STD_LOGIC_1164: Imports the STD_LOGIC_1164 package, defining the data types and operations used in the code.
ENTITY ADD8bit: Declares the entity called ADD8bit, which represents the 8-bit adder.
PORT: Defines the input and output ports of the adder:
- A, B: 8-bit input signals representing the two numbers to be added.
- Cin: Input signal for the carry-in bit.
- Y: 8-bit output signal representing the sum.
- Cout: Output signal for the carry-out bit.
ARCHITECTURE ONE OF ADD8bit: Defines the behavior of the adder in the ONE architecture.
SIGNAL: Declares internal signals:
- AA, BB: 9-bit signals (with an extra bit for the carry) used to extend the input signals A and B by adding a '0' to the left.
- temp: 9-bit signal used to store the intermediate sum of AA, BB, and Cin.
BEGIN...END ONE: The main body of the architecture, which specifies the operations:
- AA <= '0' & A; and BB <= '0' & B: Concatenate a '0' to the left of A and B to create the 9-bit signals AA and BB.
- temp <= AA + BB + Cin: Adds the extended signals AA, BB, and the carry-in Cin and stores the result in temp.
- Y <= temp(7 DOWNTO 0): Assigns the lower 8 bits of temp to the output signal Y, representing the sum.
- Cout <= temp(8): Assigns the 9th bit of temp to the output signal Cout, representing the carry-out.

This code demonstrates a simple implementation of an 8-bit adder. It can be modified to handle different data widths, include more complex operations, and be optimized for various hardware platforms.

VHDL 8-bit Adder with Carry-in and Carry-out