SystemVerilog断言验证：16位寄存器sel_reg_out的时序逻辑

assign sel_out = ({16{sel1}} & in1) | ({16{sel2}} & in2) | ({16{sel3}} & in3);\nalways @(posedge clk or negedge rst)\n if(!rst) sel_reg_out <= 'h0;\nelse sel_reg_out <= sel_out;\n\nsel_reg_out为16bit，针对该逻辑写一个SV断言内容：assert property (posedge clk) disable iff (!rst)\n (rst |=> (sel_reg_out == 'h0)) &&\n ((!rst && sel_out != 'h0) |=> sel_reg_out == sel_out);