翻译 verilog 语言always posedge CLOCK_50 begin ifmoshi==5 begin liul30 = nabeiliu10; 南北方向流量 十位 liul74 = nabeiliu10;南北方向流量 个位 liul118 = dongxiliu10;东西方向流量 十位 liul1512 = dongxiliu10; 东西

始终 @ (posedge CLOCK_50) begin

if(moshi==5) begin liul[3:0] <= nabeiliu/10; //南北方向流量 十位 liul[7:4] <= nabeiliu%10;//南北方向流量 个位 liul[11:8] <= dongxiliu/10;//东西方向流量 十位 liul[15:12] <= dongxiliu%10; //东西方向流量 个位
end else begin liul[3:0] <= moshi; liul[7:4] <= 10; liul[11:8] <= 10; liul[15:12] <= 10;
end

end

endmodule

// seg_drive 模块：用于驱动七段数码管显示数据 module seg_drive( input i_clk,

input [15:0] i_data, // 欲显数据[16

output reg [7:0] o_seg, // 段脚 output reg [3:0] o_sel // 位脚 );

//++++++++++++++++++++++++++++++++++++++ // 分频部分 开始 //++++++++++++++++++++++++++++++++++++++ reg [16:0] cnt; // 计数子

always @ (posedge i_clk) cnt <= cnt + 1'b1;

wire seg7_clk = cnt[16]; // (2^17/50M = 2.6114)ms //-------------------------------------- // 分频部分 结束 //--------------------------------------

//++++++++++++++++++++++++++++++++++++++ // 动态扫描, 生成seg7_addr 开始 //++++++++++++++++++++++++++++++++++++++ reg [1:0] seg7_addr; // 第几个seg7

always @ (posedge seg7_clk) seg7_addr <= seg7_addr + 1'b1;

always case (seg7_addr) 0 : o_sel <= 4'b0001;
1 : o_sel <= 4'b0010;
2 : o_sel <= 4'b0100;
3 : o_sel <= 4'b1000;
endcase //++++++++++++++++++++++++++++++++++++++ // 根据seg7_addr, 选择待译段码 开始 //++++++++++++++++++++++++++++++++++++++ reg [7:0] seg_data_r; // 待译段码

always case (seg7_addr) 0 : seg_data_r <= i_data[3:0]; 1 : seg_data_r <= i_data[7:4]; 2 : seg_data_r <= i_data[11:8]; 3 : seg_data_r <= i_data[15:12]; endcase

always @ (posedge i_clk) case(seg_data_r) // 无小数点 4'h0 : o_seg <= 8'hc0; 4'h1 : o_seg <= 8'hf9; 4'h2 : o_seg <= 8'ha4; 4'h3 : o_seg <= 8'hb0; 4'h4 : o_seg <= 8'h99; 4'h5 : o_seg <= 8'h92; 4'h6 : o_seg <= 8'h82; 4'h7 : o_seg <= 8'hf8; 4'h8 : o_seg <= 8'h80; 4'h9 : o_seg <= 8'h90; 4'ha : o_seg <= 8'hff; endcase

endmodule

// seg_drive2 模块：用于驱动第二个七段数码管显示数据，与seg_drive模块相同 module seg_drive2( input i_clk,

input [15:0] i_data, // 欲显数据[16

output reg [7:0] o_seg, // 段脚 output reg [3:0] o_sel // 位脚 )